first draft done

presentation.tex

@@ -134,9 +134,12 @@ showstringspaces=false            %
 
 \definecolor{darkgreen}{rgb}{0.0,0.5,0.0}
 
-\title[LoRa]{Breadboard logic}
+\title[Breadboard]{Breadboard logic}
+\author{Tobias Eckert, Simon Pirkelmann}
+\institute{\includegraphics[scale=0.5]{images/iR.pdf}}
 \date{January 13th, 2020}
 
+
 \AfterPreamble{\hypersetup{
   urlcolor=blue,
 }}
@@ -812,13 +815,13 @@ If we want to add N-bit numbers we have to account for the carry bit of lower-va
 \begin{itemize}
 \item Adding two N-bit binary numbers:\\
 	\begin{tabular}{rccccc}
-		\textbf{A}:     &   & 1 & 0 & 1 & 1 \\ 
+		\textbf{A}:     &   & 1 & 0 & 1 & 1  \\ 
 		\textbf{B}:     &   & 1 & 1 & 1 & 0 \\
 		\textbf{CARRY}: & \onslide<9->{1} & \onslide<7->{1} & \onslide<5->{1} & \onslide<3->{0} & 0 \\	\hline
 		\textbf{SUM}:   & \onslide<10->{1} & \onslide<8->{1} & \onslide<6->{0} & \onslide<4->{0} & \onslide<2->{1} 
 	\end{tabular}
 
-\item<11-> 4 bit \textbf{ripple carry adder}:\\[0.2cm]
+\item<11-> nibble \textbf{ripple carry adder}:\\[0.2cm]
 	\begin{circuitikz}[scale=0.9]
 		
 		
@@ -948,7 +951,11 @@ If we want to add N-bit numbers we have to account for the carry bit of lower-va
 \end{itemize}
 \end{frame}
 
-\begin{frame}{Gated latch}
+\begin{frame}{Gated S-R latch}
+\begin{itemize}
+	\item S-R latch should only change state when certain conditions are met (e.g. on clock pulse)
+	$\rightarrow$ gated S-R latch
+\end{itemize}
 \begin{circuitikz}
 	\draw (0,0) node[nor port] (NOR1) {{\hspace*{-0.0cm}\tiny NOR}};
 	\draw (0,-3) node[nor port] (NOR2) {{\hspace*{-0.0cm}\tiny NOR}};
@@ -988,9 +995,16 @@ If we want to add N-bit numbers we have to account for the carry bit of lower-va
 	\node[right] at (Q) {\textbf{Q}};
 	\node[right] at (Qbar) { $\overline{\mbox{\textbf{Q}}}$};
 \end{circuitikz}
+\begin{itemize}
+\item output \textbf{Q} can only change when \textbf{EN} is HIGH
+\end{itemize}
 \end{frame}
 
-\begin{frame}{D latch}
+\begin{frame}{(Transparent) D latch}
+\begin{itemize}
+	\item Problem of "forbidden" state \textbf{R} = \textbf{S} = 1 for S-R latch\\
+	$\rightarrow$ D latch prevents this from happening
+\end{itemize}
 \begin{circuitikz}
 	\draw (0,0) node[nor port] (NOR1) {{\hspace*{-0.0cm}\tiny NOR}};
 	\draw (0,-3) node[nor port] (NOR2) {{\hspace*{-0.0cm}\tiny NOR}};
@@ -1032,13 +1046,94 @@ If we want to add N-bit numbers we have to account for the carry bit of lower-va
 	\node[left] at (EN) {\textbf{EN}};
 	\node[right] at (Q) {\textbf{Q}};
 	\node[right] at (Qbar) { $\overline{\mbox{\textbf{Q}}}$};
-\end{circuitikz}
+\end{circuitikz}\\
+Symbol:\\
+\hspace{3cm}
+	\begin{circuitikz}[scale=0.15]
+		\ctikzset{chips/scale=0.75}
+		\draw (0,0) node[dipchip, num pins=4, hide numbers, no topmark, external pins width=0, align=left] (DLATCH) {{\tiny D latch}};
+		\draw (DLATCH.bpin 1) ++ (-2,0) node (D) {};
+		\draw (DLATCH.bpin 2) ++ (-2,0) node (EN) {};
+		\draw (DLATCH.bpin 4) ++ (2,0) node (Q) {};
+		\draw (DLATCH.bpin 3) ++ (2,0) node (Qbar) {};
+		
+		\draw (D) to[short, o-] (DLATCH.bpin 1);
+		\draw (EN) to[short, o-] (DLATCH.bpin 2);
+		\draw (Q) to[short, o-] (DLATCH.bpin 4);
+		\draw (Qbar) to[short, o-] (DLATCH.bpin 3);
+		
+		\node[left] at (D) {\textbf{D}};
+		\node[left] at (EN) {\textbf{EN}};
+		\node[right] at (Q) {\textbf{Q}};	
+		\node[right] at (Qbar) { $\overline{\mbox{\textbf{Q}}}$};
+	\end{circuitikz}
 \end{frame}
 
+\begin{frame}{D flip-flop}
+	\begin{itemize}
+		\item Only want the state \textbf{Q} to change at specific point in time
+		\item Implemented using two latches in master-slave configuration:
+	\end{itemize}
+	\begin{circuitikz}[scale=0.2]
+		\ctikzset{chips/scale=1.0}
 		
+		% master
+		\draw (0,0) node[dipchip, num pins=4, hide numbers, no topmark, external pins width=0, align=left] (DLATCH1) {{\tiny D latch}};
+		\draw (DLATCH1.bpin 1) ++ (-4,0) node (D1) {};
+		\draw (DLATCH1.bpin 2) ++ (-4,-6) node (EN1) {};
+		\draw (EN1) ++ (3,0) node (P1) {};
+		\draw (DLATCH1.bpin 4) ++ (2,0) node (Q1) {};
+		\draw (DLATCH1.bpin 3) ++ (2,0) node (Qbar1) {};
 		
-\begin{frame}{Building a N-bit shift register}
+		\draw (D1) to[short, o-] (DLATCH1.bpin 1);
-	content...
+		\draw (EN1) to[short, o-] (P1) |- (DLATCH1.bpin 2);
+		\draw (Q1) to[short, -] (DLATCH1.bpin 4);
+		
+		\node[left] at (D1) {\textbf{D}};
+		\node[left] at (EN1) {\textbf{CLK}};
+		\node[left] at (DLATCH1.bpin 4) {\textbf{{\tiny Q1}}};	
+		\node[left] at (DLATCH1.bpin 3) { $\overline{\mbox{\textbf{{\tiny Q1}}}}$};
+		
+		% slave
+		\draw (20,0) node[dipchip, num pins=4, hide numbers, no topmark, external pins width=0, align=left] (DLATCH2) {{\tiny D latch}};
+		\draw (DLATCH2.bpin 1) ++ (-2,0) node (D2) {};
+		\draw (DLATCH2.bpin 2) ++ (-2,0) node (EN2) {};
+		\draw (DLATCH2.bpin 4) ++ (4,0) node (Q2) {};
+		\draw (DLATCH2.bpin 3) ++ (4,0) node (Qbar2) {};
+		
+		\draw (D2) to[short, -] (DLATCH2.bpin 1);
+		\draw (EN2) to[short, -] (DLATCH2.bpin 2);
+		\draw (Q2) to[short, o-] (DLATCH2.bpin 4);
+		\draw (Qbar2) to[short, o-] (DLATCH2.bpin 3);
+		
+		\draw (Q1.center) -- (D2.center);
+		
+		\node[right] at (DLATCH2.bpin 1) {\textbf{{\tiny D2}}};
+		\node[right] at (DLATCH2.bpin 2) {$\overline{\mbox{\textbf{{\tiny CLK}}}}$};
+		\node[right] at (Q2) {\textbf{Q}};	
+		\node[right] at (Qbar2) { $\overline{\mbox{\textbf{Q}}}$};
+		
+		% inverter
+		\draw (P1) ++ (5,0) node[not port, scale=0.75] (NOT) {};
+		\draw (P1) to[short,*-] (NOT.in);
+		\draw (EN2.center) |- (NOT.out);
+		
+		\node[above] at (DLATCH1.n) {master};	
+		\node[above] at (DLATCH2.n) {slave};	
+		
+		\draw (DLATCH1.nw) ++ (-2, 2.5) node (A) {};
+		\draw (DLATCH2.ne) ++ (2, 2.5) node (B) {};
+		\draw (DLATCH2.se) ++ (2, -7) node (C) {};
+		\draw (DLATCH1.sw) ++ (-2, -7) node (D) {};
+		\draw[dashed] (A.center) -- (B.center) -- (C.center) -- (D.center) -- (A.center);
+	\end{circuitikz}
+	\begin{itemize}
+		\item \textbf{Q} changes only on falling edge of the \textbf{CLK} signal
+	\end{itemize}	
 \end{frame}
 
+%\begin{frame}{Building a N-bit shift register}
+%	content...
+%\end{frame}
+
 \end{document}