493 lines
12 KiB
TeX
493 lines
12 KiB
TeX
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\usepackage[english]{babel}
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\usepackage{tcolorbox,listings}
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\usepackage{textpos}
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\usepackage{setspace}
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\usepackage{circuitikz}
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\usetikzlibrary{positioning}
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\fvset{frame=single,framesep=1mm,fontfamily=courier,fontsize=\scriptsize,framerule=.3mm,numbersep=1mm,commandchars=\\\{\}}
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keywordstyle=\ttfamily\color{lightblue},
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spartan,
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listing only,
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listing options={style=commandline},
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breakable
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% Python environment
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{}
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basicstyle=\ttfamily\tiny,
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numbers=none,
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keywordstyle=\color{blue},
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morekeywords={{git add}},
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numbersep=2pt,
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moredelim=**[is][\color{darkgreen}]{_green_}{_green_},
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moredelim=**[is][\color{blue}]{_blue_}{_blue_},
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}
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\newtcblisting{ConsoleVerbatimTiny}{
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arc=0mm,
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top=-2mm,
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bottom=-2mm,
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left=0mm,
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right=0mm,
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width=\textwidth,
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boxrule=0.5pt,
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colupper=white,
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colback=black,
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spartan,
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listing options={style=commandline},
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breakable
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\tiny\bgroup\color{black}}{\egroup % for the emulated
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\usepackage{hyperref}
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\definecolor{darkgreen}{rgb}{0.0,0.5,0.0}
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\title[LoRa]{Breadboard logic}
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\date{January 13th, 2020}
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\AfterPreamble{\hypersetup{
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urlcolor=blue,
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}}
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\begin{document}
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\begin{frame}
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\titlepage
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\end{frame}
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% Uncomment these lines for an automatically generated outline.
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\begin{frame}{Outline}
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\tableofcontents
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\end{frame}
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\section{Boolean logic}
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\begin{frame}{Basic logic operation}
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\begin{itemize}
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\item Two states \textbf{TRUE} and \textbf{FALSE}
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(also written as \textbf{1} and \textbf{0})
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\item Boolean logic describes logical operations
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\begin{minipage}{0.5\textwidth}
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\item \textbf{NOT}
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\begin{tabular}{c|c}
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A & Y\\
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\hline
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0 & 1 \\
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1 & 0
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\end{tabular}
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\item \textbf{AND}
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\begin{tabular}{cc|c}
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A & B & Y\\
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\hline
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0 & 0 & 0 \\
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1 & 0 & 0 \\
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0 & 1 & 0 \\
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1 & 1 & 1 \\
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\end{tabular}
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\item \textbf{OR}
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\begin{tabular}{cc|c}
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A & B & Y\\
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\hline
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0 & 0 & 0 \\
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1 & 0 & 1 \\
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0 & 1 & 1 \\
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1 & 1 & 1 \\
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\end{tabular}
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\end{minipage}%
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\begin{minipage}{0.5\textwidth}
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\item \textbf{XOR}
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\begin{tabular}{cc|c}
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A & B & Y\\
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\hline
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0 & 0 & 0 \\
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1 & 0 & 1 \\
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0 & 1 & 1 \\
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1 & 1 & 0 \\
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\end{tabular}
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\item \textbf{NAND}
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\begin{tabular}{cc|c}
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A & B & Y\\
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\hline
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0 & 0 & 1 \\
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1 & 0 & 1 \\
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0 & 1 & 1 \\
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1 & 1 & 0 \\
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\end{tabular}
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\end{minipage}
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\item In electronics boolean states are represented by different voltage levels, e.g.~\textbf{FALSE} = 0 V, \textbf{TRUE} = 5 V
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\end{itemize}
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\end{frame}
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\begin{frame}{Basic gate functionality with push buttons}
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\begin{minipage}{0.3\textwidth}
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% AND gate
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\ctikzset{bipoles/resistor/height=.2}
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\textbf{AND gate}\\
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (0,-3.5) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
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\draw (0,-4.5) node[pushbuttonshape,rotate=90](B) {\textbf{B}};
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\draw (0,-1) node[](Y) {};
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\draw (0, -6) node[ground](GND) {};
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\draw (VCC) to[R] (Y) to[empty led,name=OUT] (A.east) (A.west) -- (B.east) (B.west) -- (GND);
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\node[left] at (OUT.south) {\textbf{Y}};
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\end{circuitikz}
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\end{minipage}%
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\begin{minipage}{0.3\textwidth}
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\textbf{OR gate}\\
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (-1, -3) node (TL) {};
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\draw (1, -3) node (TR) {};
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\draw ($(TL)!0.5!(TR)$) node (INT1) {};
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\draw (-1, -5) node (BL) {};
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\draw (1, -5) node (BR) {};
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\draw ($(BL)!0.5!(BR)$) node (INT2) {};
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\node (Y) at ($(VCC)!0.5!(INT1)$) {};
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\draw (0, -6) node[ground](GND) {};
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\draw ($(TL)!0.5!(BL)$) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
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\draw ($(TR)!0.5!(BR)$) node[pushbuttonshape,rotate=90](B) {\textbf{B}};
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\draw (VCC) to [R] (Y) to[empty led, name=OUT] (INT1.center);
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\draw (INT1.center) -- (TL.center);
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\draw (INT1.center) -- (TR.center);
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\draw (TL.center) -- (A) -- (BL.center);
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\draw (TR.center) -- (B) -- (BR.center);
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\draw (BR.center) -- (INT2.center);
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\draw (BL.center) -- (INT2.center);
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\draw (INT2.center) -- (GND);
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\node[left] at (OUT.south) {\textbf{Y}};
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\end{circuitikz}
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\end{minipage}
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\begin{minipage}{0.3\textwidth}
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\textbf{NOT gate\\ (inverter)}\\
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (-1, -3) node (TL) {};
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\draw (1, -3) node (TR) {};
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\draw ($(TL)!0.5!(TR)$) node (INT1) {};
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\draw (-1, -5) node (BL) {};
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\draw (1, -5) node (BR) {};
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\draw ($(BL)!0.5!(BR)$) node (INT2) {};
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\draw (0, -6) node[ground](GND) {};
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\draw ($(TL)!0.5!(BL)$) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
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\draw ($(TR)!0.5!(BR)$) node[emptylediodeshape, rotate=-90](B) {};
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\draw (VCC) to[R] (INT1.center);
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\draw (INT1.center) -- (TL.center);
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\draw (INT1.center) -- (TR.center);
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\draw (TL.center) -- (A) -- (BL.center);
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\draw (TR.center) -- (B) -- (BR.center);
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\draw (BR.center) -- (INT2.center);
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\draw (BL.center) -- (INT2.center);
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\draw (INT2.center) -- (GND);
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\node[left] at (B.south) {\textbf{Y}};
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\end{circuitikz}
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\end{minipage}
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\end{frame}
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\begin{frame}{Breadboard}
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\vspace{1cm}
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\begin{overlayarea}{\textwidth}{\textheight}
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\begin{flushleft}
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\includegraphics[scale=0.45]{images/Breadboard.jpg}\\
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\includegraphics<2>[scale=0.5]{images/Breadboard-Pinout.png}
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\end{flushleft}
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\end{overlayarea}
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\end{frame}
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\begin{frame}{Basic gates with transistors}
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\begin{overlayarea}{\textwidth}{\textheight}
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\textbf{AND gate}\\
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\begin{minipage}{0.4\textwidth}
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\only<1>{
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (0,-3.5) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
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\draw (0,-4.5) node[pushbuttonshape,rotate=90](B) {\textbf{B}};
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\draw (0,-1) node[](Y) {};
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\draw (0, -6) node[ground](GND) {};
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\draw (VCC) to[R] (Y) to[empty led,name=OUT] (A.east) (A.west) -- (B.east) (B.west) -- (GND);
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\node[left] at (OUT.south) {\textbf{Y}};
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\end{circuitikz}
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}
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\only<2>{
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (-3, -3) node (A) {};
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\draw (-3, -4.5) node (B) {};
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\draw (0,-3) node[npn](P1) {};
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\draw (0,-4.5) node[npn](P2) {};
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\draw (0, -5.5) node[ground](GND) {};
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\draw (A) to[R,o-] (P1.B);
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\draw (B) to[R,o-] (P2.B);
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\draw (VCC) to[R] (0,-1.75) to[empty led, name=OUT] (P1.C) (P1.E) -- (P2.C) (P2.E) -- (GND);
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\node[left] at (A) {\textbf{A}};
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\node[left] at (B) {\textbf{B}};
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\node[right] at (OUT.nw) {\textbf{Y}};
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\end{circuitikz}
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}
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\only<3->{
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (-3, -3) node (A) {};
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\draw (-3, -4.5) node (B) {};
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\draw (2, -1.75) node (Y) {};
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\draw (0,-3) node[npn](P1) {};
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\draw (0,-4.5) node[npn](P2) {};
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\draw (0, -5.5) node[ground](GND) {};
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\draw (A) to[R,o-] (P1.B);
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\draw (B) to[R,o-] (P2.B);
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\draw (VCC) to[R] (0,-1.75) -- (P1.C) (P1.E) -- (P2.C) (P2.E) -- (GND);
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\draw (0,-1.75) to[short,-o] (Y);
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\node[left] at (A) {\textbf{A}};
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\node[left] at (B) {\textbf{B}};
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\node[right] at (Y) {\textbf{Y}};
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\end{circuitikz}
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}
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\end{minipage}%
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\begin{minipage}{0.4\textwidth}
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\vspace{3cm}
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\only<4>{
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{Symbol}:
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\begin{circuitikz}
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\draw (0,0) node[and port] (AND) {};
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\draw (AND.in 1) ++ (-1,0) node (A) {};
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\draw (AND.in 2) ++ (-1,0) node (B) {};
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\draw (AND.out) ++ (1,0) node (Y) {};
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\draw (AND.in 1) to[short,-o] (A);
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\draw (AND.in 2) to[short,-o] (B);
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\draw (AND.out) to[short,-o] (Y);
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\node[left] at (A) {\textbf{A}};
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\node[left] at (B) {\textbf{B}};
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\node[right] at (Y) {\textbf{Y}};
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\end{circuitikz}
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}
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\end{minipage}
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\end{overlayarea}
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\end{frame}
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\begin{frame}{Basic gates with transistors}
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\begin{minipage}{0.5\textwidth}
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\textbf{OR gate}\\
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (-1, -3) node (TL) {};
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\draw (1, -3) node (TR) {};
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\draw ($(TL)!0.5!(TR)$) node (INT1) {};
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\draw (-1, -5.5) node (BL) {};
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\draw (1, -5.5) node (BR) {};
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\draw ($(BL)!0.5!(BR)$) node (INT2) {};
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\node (Y) at ($(VCC)!0.5!(INT1)$) {};
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\draw (0, -6) node[ground](GND) {};
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\draw ($(TL)!0.3!(BL)$) node[npn](P1) {};
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\draw ([xshift=-3cm]P1) node[] (A) {};
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\draw ($(TR)!0.7!(BR)$) node[npn](P2) {};
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\draw ([xshift=-5cm]P2) node (B) {};
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\draw (VCC) to [R] (Y) to[empty led, name=OUT] (INT1.center);
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\draw (INT1.center) -- (TL.center);
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\draw (INT1.center) -- (TR.center);
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\draw (TL.center) -- (P1.C) (P1.E) -- (BL.center);
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\draw (TR.center) -- (P2.C) (P2.E) -- (BR.center);
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\draw (BR.center) -- (INT2.center);
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\draw (BL.center) -- (INT2.center);
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\draw (INT2.center) -- (GND);
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\draw (A) to[R,o-] (P1.B);
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\draw (B) to[R,o-] (P2.B);
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\node[left] at (A) {\textbf{A}};
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\node[left] at (B) {\textbf{B}};
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\node[left] at (OUT.south) {\textbf{Y}};
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\end{circuitikz}
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\end{minipage}
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\end{frame}
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\begin{frame}
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\begin{minipage}{0.5\textwidth}
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\textbf{NOT gate\\ (inverter)}\\
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\begin{circuitikz}
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\draw (0,0) node[vcc](VCC){5 V};
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\draw (-1, -3) node (TL) {};
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\draw (1, -3) node (TR) {};
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\draw ($(TL)!0.5!(TR)$) node (INT1) {};
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\draw (-1, -5) node (BL) {};
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\draw (1, -5) node (BR) {};
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\draw ($(BL)!0.5!(BR)$) node (INT2) {};
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\draw (0, -6) node[ground](GND) {};
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\draw ($(TL)!0.5!(BL)$) node[npn](P1) {};
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\draw ([xshift=-3cm]P1) node[] (A) {};
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\draw ($(TR)!0.5!(BR)$) node[emptylediodeshape, rotate=-90](B) {};
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\draw (VCC) to[R] (INT1.center);
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\draw (INT1.center) -- (TL.center);
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\draw (INT1.center) -- (TR.center);
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\draw (TL.center) -- (P1.C) (P1.E) -- (BL.center);
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\draw (TR.center) -- (B) -- (BR.center);
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\draw (BR.center) -- (INT2.center);
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\draw (BL.center) -- (INT2.center);
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\draw (INT2.center) -- (GND);
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\draw (A) to[R,o-] (P1.B);
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\node[left] at (A) {\textbf{A}};
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\node[left] at (B.south) {\textbf{Y}};
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\end{circuitikz}
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\end{minipage}
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\end{frame}
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\begin{frame}{Building some gates with other gates}
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content...
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\end{frame}
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\section{What can we do with logic gates}
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\begin{frame}{Binary addition}
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Adding two bits\\
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can be implemented with one AND gate and one XOR gate
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\end{frame}
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\begin{frame}{Full Adder}
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content...
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\end{frame}
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\begin{frame}{Building a N-bit adder}
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Ripple carry adder
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\end{frame}
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\begin{frame}{Memory}
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S-R-Latch
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\end{frame}
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\begin{frame}{Gated latch}
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content...
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\end{frame}
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\begin{frame}{D latch}
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content...
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\end{frame}
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\section{Latches and Flip-Flops}
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\begin{frame}{Building a N-bit shift register}
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content...
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\end{frame}
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\end{document}
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