Add some notes for part 2

Part 2 notes.md

@@ -0,0 +1,60 @@
+# Part 2 notes
+
+- Lots of rules for symbols/footprints to be included in official libraries: [Kicad Library Conventions][KLC]
+- Not that important for project-specific libraries, but still good to make a best effort
+- Defaults of numeric values usually satisfy the KLC (e.g. text field size, pin name offset
+- Libraries are grouped by functionality (e.g. resistors), then subdivided if they contain a lot of parts (>250)
+
+## Symbols
+
+- Origin should be (mostly) centered on the middle
+- Pins must be on a 100 mil grid
+- Pin numbers must match the datasheet
+- Duplicated pins (e.g. GND, VCC) should be placed together, with all but the lowest-numbered hidden
+  - Hidden power pins must be passive
+- Grouping is by functions
+  - Input on the left
+  - Output on the right
+  - Power on top/bottom, depending on polarity
+- Electrical type must match
+- Inversion through name
+- FP assoc:
+  - For atomic symbols (those with an associated default footprint), the Footprint field must be filled with a valid entry of the format <footprint_library>:<footprint_name>.
+  - For generic symbols (those which map to multiple possible footprints), the Footprint field must be left blank
+- FP filters and metadata are things that exist
+
+## Footprints
+
+- Names:
+  - Package type (`QFN` for quad flat no-lead packages, `C` for capacitors)
+  - Name and number of pins are separated by a hypen (`TO-90`, `QFN-48`)
+  - Specific pads add identifiers to the pin count field
+    - Exposed pads: `[count]EP`
+    - e.g. `DFN-6-1EP_2x2mm_P0.5mm_EP0.61x1.42mm`
+  - Dimensions as `length x width` (height is optional)
+    - `3.5x3.5x0.2mm`
+  - Pin layout (`1x10`, `2x15`)
+  - Pitch with P (`P1.27mm`)
+  - Many other rules
+  - Often useful, [naming schemes for specific parts](https://klc.kicad.org/footprint/f3/)
+- General requirements:
+  - Datasheet usually takes priority
+  - Pin 1 should be in the top left corner
+- Silkscreen
+  - Reference must be on here (1mm size, 0.15mm thickness)
+  - Lines should be 0.12 mm
+  - Not over exposed copper
+  - Fully visible after assembly (for SMD)
+  - Pin 1 is marked
+- Fabrication layer
+  - Simplified outline
+  - Pin 1 is shown (bevel for ICs, arrow for connectors)
+  - Component value is shown here
+  - Second copy of reference (`${REFERENCE}`)
+- Courtyard
+  - 0.05 mm line width
+  - 0.01 mm grid
+  - Clearance should be 0.25 mm (or 0.15 mm for parts smaller than 0603)
+  - Some other clearance rules for specific component types
+
+[KLC]: https://klc.kicad.org/