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presentation.pdf
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492
presentation.tex
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presentation.tex
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\documentclass{beamer}
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%
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% Choose how your presentation looks.
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%
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% For more themes, color themes and font themes, see:
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% http://deic.uab.es/~iblanes/beamer_gallery/index_by_theme.html
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%
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{
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% Python style for highlighting
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emph={MyClass,__init__}, % Custom highlighting
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{
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|
||||
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\end{textblock*}}
|
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|
||||
|
||||
|
||||
\definecolor{darkgreen}{rgb}{0.0,0.5,0.0}
|
||||
|
||||
\title[LoRa]{Breadboard logic}
|
||||
\date{January 13th, 2020}
|
||||
|
||||
\AfterPreamble{\hypersetup{
|
||||
urlcolor=blue,
|
||||
}}
|
||||
|
||||
\begin{document}
|
||||
|
||||
\begin{frame}
|
||||
\titlepage
|
||||
\end{frame}
|
||||
|
||||
% Uncomment these lines for an automatically generated outline.
|
||||
\begin{frame}{Outline}
|
||||
\tableofcontents
|
||||
\end{frame}
|
||||
|
||||
|
||||
|
||||
\section{Boolean logic}
|
||||
\begin{frame}{Basic logic operation}
|
||||
\begin{itemize}
|
||||
\item Two states \textbf{TRUE} and \textbf{FALSE}
|
||||
(also written as \textbf{1} and \textbf{0})
|
||||
\item Boolean logic describes logical operations
|
||||
|
||||
\begin{minipage}{0.5\textwidth}
|
||||
\item \textbf{NOT}
|
||||
\begin{tabular}{c|c}
|
||||
A & Y\\
|
||||
\hline
|
||||
0 & 1 \\
|
||||
1 & 0
|
||||
\end{tabular}
|
||||
\item \textbf{AND}
|
||||
\begin{tabular}{cc|c}
|
||||
A & B & Y\\
|
||||
\hline
|
||||
0 & 0 & 0 \\
|
||||
1 & 0 & 0 \\
|
||||
0 & 1 & 0 \\
|
||||
1 & 1 & 1 \\
|
||||
\end{tabular}
|
||||
\item \textbf{OR}
|
||||
\begin{tabular}{cc|c}
|
||||
A & B & Y\\
|
||||
\hline
|
||||
0 & 0 & 0 \\
|
||||
1 & 0 & 1 \\
|
||||
0 & 1 & 1 \\
|
||||
1 & 1 & 1 \\
|
||||
\end{tabular}
|
||||
\end{minipage}%
|
||||
\begin{minipage}{0.5\textwidth}
|
||||
\item \textbf{XOR}
|
||||
\begin{tabular}{cc|c}
|
||||
A & B & Y\\
|
||||
\hline
|
||||
0 & 0 & 0 \\
|
||||
1 & 0 & 1 \\
|
||||
0 & 1 & 1 \\
|
||||
1 & 1 & 0 \\
|
||||
\end{tabular}
|
||||
\item \textbf{NAND}
|
||||
\begin{tabular}{cc|c}
|
||||
A & B & Y\\
|
||||
\hline
|
||||
0 & 0 & 1 \\
|
||||
1 & 0 & 1 \\
|
||||
0 & 1 & 1 \\
|
||||
1 & 1 & 0 \\
|
||||
\end{tabular}
|
||||
\end{minipage}
|
||||
\item In electronics boolean states are represented by different voltage levels, e.g.~\textbf{FALSE} = 0 V, \textbf{TRUE} = 5 V
|
||||
\end{itemize}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Basic gate functionality with push buttons}
|
||||
\begin{minipage}{0.3\textwidth}
|
||||
% AND gate
|
||||
\ctikzset{bipoles/resistor/height=.2}
|
||||
\textbf{AND gate}\\
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
\draw (0,-3.5) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
|
||||
\draw (0,-4.5) node[pushbuttonshape,rotate=90](B) {\textbf{B}};
|
||||
\draw (0,-1) node[](Y) {};
|
||||
\draw (0, -6) node[ground](GND) {};
|
||||
|
||||
\draw (VCC) to[R] (Y) to[empty led,name=OUT] (A.east) (A.west) -- (B.east) (B.west) -- (GND);
|
||||
\node[left] at (OUT.south) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
\end{minipage}%
|
||||
\begin{minipage}{0.3\textwidth}
|
||||
\textbf{OR gate}\\
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
|
||||
\draw (-1, -3) node (TL) {};
|
||||
\draw (1, -3) node (TR) {};
|
||||
\draw ($(TL)!0.5!(TR)$) node (INT1) {};
|
||||
\draw (-1, -5) node (BL) {};
|
||||
\draw (1, -5) node (BR) {};
|
||||
\draw ($(BL)!0.5!(BR)$) node (INT2) {};
|
||||
|
||||
\node (Y) at ($(VCC)!0.5!(INT1)$) {};
|
||||
|
||||
\draw (0, -6) node[ground](GND) {};
|
||||
|
||||
\draw ($(TL)!0.5!(BL)$) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
|
||||
\draw ($(TR)!0.5!(BR)$) node[pushbuttonshape,rotate=90](B) {\textbf{B}};
|
||||
|
||||
\draw (VCC) to [R] (Y) to[empty led, name=OUT] (INT1.center);
|
||||
\draw (INT1.center) -- (TL.center);
|
||||
\draw (INT1.center) -- (TR.center);
|
||||
\draw (TL.center) -- (A) -- (BL.center);
|
||||
\draw (TR.center) -- (B) -- (BR.center);
|
||||
\draw (BR.center) -- (INT2.center);
|
||||
\draw (BL.center) -- (INT2.center);
|
||||
\draw (INT2.center) -- (GND);
|
||||
|
||||
\node[left] at (OUT.south) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
\end{minipage}
|
||||
\begin{minipage}{0.3\textwidth}
|
||||
\textbf{NOT gate\\ (inverter)}\\
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
|
||||
\draw (-1, -3) node (TL) {};
|
||||
\draw (1, -3) node (TR) {};
|
||||
\draw ($(TL)!0.5!(TR)$) node (INT1) {};
|
||||
\draw (-1, -5) node (BL) {};
|
||||
\draw (1, -5) node (BR) {};
|
||||
\draw ($(BL)!0.5!(BR)$) node (INT2) {};
|
||||
|
||||
\draw (0, -6) node[ground](GND) {};
|
||||
|
||||
\draw ($(TL)!0.5!(BL)$) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
|
||||
\draw ($(TR)!0.5!(BR)$) node[emptylediodeshape, rotate=-90](B) {};
|
||||
|
||||
\draw (VCC) to[R] (INT1.center);
|
||||
\draw (INT1.center) -- (TL.center);
|
||||
\draw (INT1.center) -- (TR.center);
|
||||
\draw (TL.center) -- (A) -- (BL.center);
|
||||
\draw (TR.center) -- (B) -- (BR.center);
|
||||
\draw (BR.center) -- (INT2.center);
|
||||
\draw (BL.center) -- (INT2.center);
|
||||
\draw (INT2.center) -- (GND);
|
||||
|
||||
\node[left] at (B.south) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
\end{minipage}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Breadboard}
|
||||
\vspace{1cm}
|
||||
\begin{overlayarea}{\textwidth}{\textheight}
|
||||
\begin{flushleft}
|
||||
\includegraphics[scale=0.45]{images/Breadboard.jpg}\\
|
||||
\includegraphics<2>[scale=0.5]{images/Breadboard-Pinout.png}
|
||||
\end{flushleft}
|
||||
\end{overlayarea}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Basic gates with transistors}
|
||||
\begin{overlayarea}{\textwidth}{\textheight}
|
||||
\textbf{AND gate}\\
|
||||
\begin{minipage}{0.4\textwidth}
|
||||
\only<1>{
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
\draw (0,-3.5) node[pushbuttonshape,rotate=90](A) {\textbf{A}};
|
||||
\draw (0,-4.5) node[pushbuttonshape,rotate=90](B) {\textbf{B}};
|
||||
\draw (0,-1) node[](Y) {};
|
||||
\draw (0, -6) node[ground](GND) {};
|
||||
|
||||
\draw (VCC) to[R] (Y) to[empty led,name=OUT] (A.east) (A.west) -- (B.east) (B.west) -- (GND);
|
||||
\node[left] at (OUT.south) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
}
|
||||
\only<2>{
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
\draw (-3, -3) node (A) {};
|
||||
\draw (-3, -4.5) node (B) {};
|
||||
\draw (0,-3) node[npn](P1) {};
|
||||
\draw (0,-4.5) node[npn](P2) {};
|
||||
\draw (0, -5.5) node[ground](GND) {};
|
||||
|
||||
\draw (A) to[R,o-] (P1.B);
|
||||
\draw (B) to[R,o-] (P2.B);
|
||||
\draw (VCC) to[R] (0,-1.75) to[empty led, name=OUT] (P1.C) (P1.E) -- (P2.C) (P2.E) -- (GND);
|
||||
\node[left] at (A) {\textbf{A}};
|
||||
\node[left] at (B) {\textbf{B}};
|
||||
\node[right] at (OUT.nw) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
}
|
||||
\only<3->{
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
\draw (-3, -3) node (A) {};
|
||||
\draw (-3, -4.5) node (B) {};
|
||||
\draw (2, -1.75) node (Y) {};
|
||||
\draw (0,-3) node[npn](P1) {};
|
||||
\draw (0,-4.5) node[npn](P2) {};
|
||||
\draw (0, -5.5) node[ground](GND) {};
|
||||
|
||||
\draw (A) to[R,o-] (P1.B);
|
||||
\draw (B) to[R,o-] (P2.B);
|
||||
\draw (VCC) to[R] (0,-1.75) -- (P1.C) (P1.E) -- (P2.C) (P2.E) -- (GND);
|
||||
\draw (0,-1.75) to[short,-o] (Y);
|
||||
\node[left] at (A) {\textbf{A}};
|
||||
\node[left] at (B) {\textbf{B}};
|
||||
\node[right] at (Y) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
}
|
||||
\end{minipage}%
|
||||
\begin{minipage}{0.4\textwidth}
|
||||
\vspace{3cm}
|
||||
\only<4>{
|
||||
{Symbol}:
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[and port] (AND) {};
|
||||
\draw (AND.in 1) ++ (-1,0) node (A) {};
|
||||
\draw (AND.in 2) ++ (-1,0) node (B) {};
|
||||
\draw (AND.out) ++ (1,0) node (Y) {};
|
||||
\draw (AND.in 1) to[short,-o] (A);
|
||||
\draw (AND.in 2) to[short,-o] (B);
|
||||
\draw (AND.out) to[short,-o] (Y);
|
||||
|
||||
\node[left] at (A) {\textbf{A}};
|
||||
\node[left] at (B) {\textbf{B}};
|
||||
\node[right] at (Y) {\textbf{Y}};
|
||||
|
||||
\end{circuitikz}
|
||||
}
|
||||
\end{minipage}
|
||||
\end{overlayarea}
|
||||
\end{frame}
|
||||
\begin{frame}{Basic gates with transistors}
|
||||
\begin{minipage}{0.5\textwidth}
|
||||
\textbf{OR gate}\\
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
|
||||
\draw (-1, -3) node (TL) {};
|
||||
\draw (1, -3) node (TR) {};
|
||||
\draw ($(TL)!0.5!(TR)$) node (INT1) {};
|
||||
\draw (-1, -5.5) node (BL) {};
|
||||
\draw (1, -5.5) node (BR) {};
|
||||
\draw ($(BL)!0.5!(BR)$) node (INT2) {};
|
||||
|
||||
\node (Y) at ($(VCC)!0.5!(INT1)$) {};
|
||||
|
||||
\draw (0, -6) node[ground](GND) {};
|
||||
|
||||
\draw ($(TL)!0.3!(BL)$) node[npn](P1) {};
|
||||
\draw ([xshift=-3cm]P1) node[] (A) {};
|
||||
|
||||
\draw ($(TR)!0.7!(BR)$) node[npn](P2) {};
|
||||
\draw ([xshift=-5cm]P2) node (B) {};
|
||||
|
||||
\draw (VCC) to [R] (Y) to[empty led, name=OUT] (INT1.center);
|
||||
\draw (INT1.center) -- (TL.center);
|
||||
\draw (INT1.center) -- (TR.center);
|
||||
\draw (TL.center) -- (P1.C) (P1.E) -- (BL.center);
|
||||
\draw (TR.center) -- (P2.C) (P2.E) -- (BR.center);
|
||||
\draw (BR.center) -- (INT2.center);
|
||||
\draw (BL.center) -- (INT2.center);
|
||||
\draw (INT2.center) -- (GND);
|
||||
\draw (A) to[R,o-] (P1.B);
|
||||
\draw (B) to[R,o-] (P2.B);
|
||||
|
||||
\node[left] at (A) {\textbf{A}};
|
||||
\node[left] at (B) {\textbf{B}};
|
||||
\node[left] at (OUT.south) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
\end{minipage}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}
|
||||
|
||||
\begin{minipage}{0.5\textwidth}
|
||||
\textbf{NOT gate\\ (inverter)}\\
|
||||
\begin{circuitikz}
|
||||
\draw (0,0) node[vcc](VCC){5 V};
|
||||
|
||||
\draw (-1, -3) node (TL) {};
|
||||
\draw (1, -3) node (TR) {};
|
||||
\draw ($(TL)!0.5!(TR)$) node (INT1) {};
|
||||
\draw (-1, -5) node (BL) {};
|
||||
\draw (1, -5) node (BR) {};
|
||||
\draw ($(BL)!0.5!(BR)$) node (INT2) {};
|
||||
|
||||
\draw (0, -6) node[ground](GND) {};
|
||||
|
||||
\draw ($(TL)!0.5!(BL)$) node[npn](P1) {};
|
||||
\draw ([xshift=-3cm]P1) node[] (A) {};
|
||||
|
||||
\draw ($(TR)!0.5!(BR)$) node[emptylediodeshape, rotate=-90](B) {};
|
||||
|
||||
\draw (VCC) to[R] (INT1.center);
|
||||
\draw (INT1.center) -- (TL.center);
|
||||
\draw (INT1.center) -- (TR.center);
|
||||
\draw (TL.center) -- (P1.C) (P1.E) -- (BL.center);
|
||||
\draw (TR.center) -- (B) -- (BR.center);
|
||||
\draw (BR.center) -- (INT2.center);
|
||||
\draw (BL.center) -- (INT2.center);
|
||||
\draw (INT2.center) -- (GND);
|
||||
|
||||
\draw (A) to[R,o-] (P1.B);
|
||||
\node[left] at (A) {\textbf{A}};
|
||||
\node[left] at (B.south) {\textbf{Y}};
|
||||
\end{circuitikz}
|
||||
\end{minipage}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Building some gates with other gates}
|
||||
content...
|
||||
\end{frame}
|
||||
|
||||
\section{What can we do with logic gates}
|
||||
\begin{frame}{Binary addition}
|
||||
Adding two bits\\
|
||||
can be implemented with one AND gate and one XOR gate
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Full Adder}
|
||||
content...
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Building a N-bit adder}
|
||||
Ripple carry adder
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Memory}
|
||||
S-R-Latch
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Gated latch}
|
||||
content...
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{D latch}
|
||||
content...
|
||||
\end{frame}
|
||||
|
||||
\section{Latches and Flip-Flops}
|
||||
|
||||
\begin{frame}{Building a N-bit shift register}
|
||||
content...
|
||||
\end{frame}
|
||||
|
||||
\end{document}
|
||||
Loading…
Reference in New Issue
Block a user