Initial commit

main
Valentin Ochs 2021-11-05 17:43:28 +01:00
commit 26e8d5119b
11 changed files with 11054 additions and 0 deletions

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# For PCBs designed using KiCad: http://www.kicad-pcb.org/
# Format documentation: http://kicad-pcb.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv

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adder-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 74xGxx_74LVC1G79
#
DEF 74xGxx_74LVC1G79 U 0 40 Y Y 1 F N
F0 "U" -100 200 50 H V C CNN
F1 "74xGxx_74LVC1G79" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74AUC1G79 74AUP1G79
$FPLIST
SOT*
SG*
$ENDFPLIST
DRAW
S -150 150 150 -150 0 1 10 N
X D 1 -250 100 100 R 40 40 1 1 I
X C 2 -250 -100 100 R 40 40 1 1 I C
X GND 3 0 -150 0 D 40 40 1 1 W N
X Q 4 250 100 100 L 40 40 1 1 O
X VCC 5 0 150 0 U 40 40 1 1 W N
ENDDRAW
ENDDEF
#
# Connector_Conn_01x04_Female
#
DEF Connector_Conn_01x04_Female J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Conn_01x04_Female" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
A 0 100 20 901 -901 1 1 6 N 0 120 0 80
P 2 1 1 6 -50 -200 -20 -200 N
P 2 1 1 6 -50 -100 -20 -100 N
P 2 1 1 6 -50 0 -20 0 N
P 2 1 1 6 -50 100 -20 100 N
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
X Pin_4 4 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Conn_01x04_Male
#
DEF Connector_Conn_01x04_Male J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Conn_01x04_Male" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S 34 -195 0 -205 1 1 6 F
S 34 -95 0 -105 1 1 6 F
S 34 5 0 -5 1 1 6 F
S 34 105 0 95 1 1 6 F
P 2 1 1 6 50 -200 34 -200 N
P 2 1 1 6 50 -100 34 -100 N
P 2 1 1 6 50 0 34 0 N
P 2 1 1 6 50 100 34 100 N
X Pin_1 1 200 100 150 L 50 50 1 1 P
X Pin_2 2 200 0 150 L 50 50 1 1 P
X Pin_3 3 200 -100 150 L 50 50 1 1 P
X Pin_4 4 200 -200 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Q_NMOS_GSD
#
DEF Device_Q_NMOS_GSD Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Device_Q_NMOS_GSD" 200 -50 50 H V L CNN
F2 "" 200 100 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 65 0 110 0 1 10 N
C 100 -70 10 0 1 0 F
C 100 70 10 0 1 0 F
P 2 0 1 0 10 0 -100 0 N
P 2 0 1 10 10 75 10 -75 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 0 100 -100 100 0 30 0 N
P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
P 4 0 1 0 110 20 115 15 145 15 150 10 N
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
X G 1 -200 0 100 R 50 50 1 1 I
X S 2 100 -200 100 U 50 50 1 1 P
X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Q_PMOS_GSD
#
DEF Device_Q_PMOS_GSD Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Device_Q_PMOS_GSD" 200 -50 50 H V L CNN
F2 "" 200 100 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 65 0 110 0 1 10 N
C 100 -70 10 0 1 0 F
C 100 70 10 0 1 0 F
P 2 0 1 0 10 0 -100 0 N
P 2 0 1 10 10 75 10 -75 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 0 100 -100 100 0 30 0 N
P 4 0 1 0 30 70 130 70 130 -70 30 -70 N
P 4 0 1 0 90 0 50 15 50 -15 90 0 F
P 4 0 1 0 110 -20 115 -15 145 -15 150 -10 N
P 4 0 1 0 130 -15 115 10 145 10 130 -15 N
X G 1 -200 0 100 R 50 50 1 1 I
X S 2 100 -200 100 U 50 50 1 1 P
X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Switch_SW_SPDT
#
DEF Switch_SW_SPDT SW 0 0 Y N 1 F N
F0 "SW" 0 170 50 H V C CNN
F1 "Switch_SW_SPDT" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -80 0 20 0 0 0 N
C 80 -100 20 0 0 0 N
C 80 100 20 0 1 0 N
P 2 0 1 0 -60 10 65 90 N
X A 1 200 100 100 L 50 50 1 1 P
X B 2 -200 0 100 R 50 50 1 1 P
X C 3 200 -100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VDD
#
DEF power_VDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VDD" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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(module AlignmentHole_3.2mm_M3 (layer F.Cu) (tedit 6184EC98)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(attr virtual)
(fp_text reference REF** (at 0 -4.2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value AlignmentHole_3.2mm_M3 (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Paste *.Mask))
)

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(module LOGO (layer F.Cu)
(at 0 0)
(fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.3)))
)
(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
(effects (font (thickness 0.3)))
)
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(xy -3.493269 -0.843363) (xy -3.268402 -0.891021) (xy -3.050124 -0.871424) )(layer F.SilkS) (width 0.010000)
)
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)
(fp_poly (pts (xy -2.345148 -2.721045) (xy -2.244151 -2.639159) (xy -2.204767 -2.520975) (xy -2.231431 -2.381457) (xy -2.328579 -2.235573) (xy -2.345267 -2.218266) (xy -2.491020 -2.112579) (xy -2.641541 -2.071200)
(xy -2.777731 -2.096641) (xy -2.850939 -2.151750) (xy -2.917827 -2.279728) (xy -2.916555 -2.420553) (xy -2.857707 -2.555960) (xy -2.751867 -2.667684) (xy -2.609619 -2.737459) (xy -2.503324 -2.751666)
(xy -2.345148 -2.721045) )(layer F.SilkS) (width 0.010000)
)
)

239
adder.pro Normal file
View File

@ -0,0 +1,239 @@
update=Sun 31 Oct 2021 04:47:34 PM CET
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.5
ViaDiameter1=0.6
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=1
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

1220
adder.sch Normal file

File diff suppressed because it is too large Load Diff

111
buffer.sch Normal file
View File

@ -0,0 +1,111 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 9 43
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L 74xGxx:74LVC1G79 U?
U 1 1 617F83E0
P 5600 3800
AR Path="/617F83E0" Ref="U?" Part="1"
AR Path="/617F77F8/617F83E0" Ref="U1" Part="1"
AR Path="/617F9D75/617F83E0" Ref="U2" Part="1"
AR Path="/617FB4EC/617F83E0" Ref="U3" Part="1"
AR Path="/618026B5/617F83E0" Ref="U4" Part="1"
AR Path="/61802BAA/617F83E0" Ref="U5" Part="1"
AR Path="/617F0BFE/617F83E0" Ref="U6" Part="1"
AR Path="/6180F852/617F83E0" Ref="U7" Part="1"
AR Path="/61827E85/617F83E0" Ref="U8" Part="1"
AR Path="/6187BF05/617F83E0" Ref="U9" Part="1"
AR Path="/6189E1B8/617F83E0" Ref="U10" Part="1"
AR Path="/618AD774/617F83E0" Ref="U11" Part="1"
AR Path="/618BDD8A/617F83E0" Ref="U12" Part="1"
AR Path="/6191B1A4/617F83E0" Ref="U13" Part="1"
AR Path="/61921364/617F83E0" Ref="U14" Part="1"
AR Path="/61962662/617F83E0" Ref="U?" Part="1"
AR Path="/6196C12E/617F83E0" Ref="U15" Part="1"
F 0 "U15" H 5600 4117 50 0000 C CNN
F 1 "B" H 5600 4026 50 0000 C CNN
F 2 "Package_TO_SOT_SMD:SOT-353_SC-70-5" H 5600 3800 50 0001 C CNN
F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 5600 3800 50 0001 C CNN
1 5600 3800
1 0 0 -1
$EndComp
Wire Wire Line
5350 3900 5150 3900
$Comp
L power:GND #PWR?
U 1 1 617F83E9
P 5600 3950
AR Path="/617F83E9" Ref="#PWR?" Part="1"
AR Path="/617F77F8/617F83E9" Ref="#PWR0103" Part="1"
AR Path="/617F9D75/617F83E9" Ref="#PWR0105" Part="1"
AR Path="/617FB4EC/617F83E9" Ref="#PWR0107" Part="1"
AR Path="/618026B5/617F83E9" Ref="#PWR0109" Part="1"
AR Path="/61802BAA/617F83E9" Ref="#PWR0111" Part="1"
AR Path="/617F0BFE/617F83E9" Ref="#PWR0129" Part="1"
AR Path="/6180F852/617F83E9" Ref="#PWR0131" Part="1"
AR Path="/61827E85/617F83E9" Ref="#PWR0133" Part="1"
AR Path="/6187BF05/617F83E9" Ref="#PWR0135" Part="1"
AR Path="/6189E1B8/617F83E9" Ref="#PWR0137" Part="1"
AR Path="/618AD774/617F83E9" Ref="#PWR0139" Part="1"
AR Path="/618BDD8A/617F83E9" Ref="#PWR0141" Part="1"
AR Path="/6191B1A4/617F83E9" Ref="#PWR0143" Part="1"
AR Path="/61921364/617F83E9" Ref="#PWR0145" Part="1"
AR Path="/61962662/617F83E9" Ref="#PWR?" Part="1"
AR Path="/6196C12E/617F83E9" Ref="#PWR0147" Part="1"
F 0 "#PWR0147" H 5600 3700 50 0001 C CNN
F 1 "GND" H 5605 3777 50 0000 C CNN
F 2 "" H 5600 3950 50 0001 C CNN
F 3 "" H 5600 3950 50 0001 C CNN
1 5600 3950
1 0 0 -1
$EndComp
Wire Wire Line
5600 3400 5600 3650
Wire Wire Line
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$Comp
L power:VDD #PWR0104
U 1 1 617F880C
P 5600 3400
AR Path="/617F77F8/617F880C" Ref="#PWR0104" Part="1"
AR Path="/617F9D75/617F880C" Ref="#PWR0106" Part="1"
AR Path="/617FB4EC/617F880C" Ref="#PWR0108" Part="1"
AR Path="/618026B5/617F880C" Ref="#PWR0110" Part="1"
AR Path="/61802BAA/617F880C" Ref="#PWR0112" Part="1"
AR Path="/617F0BFE/617F880C" Ref="#PWR0130" Part="1"
AR Path="/6180F852/617F880C" Ref="#PWR0132" Part="1"
AR Path="/61827E85/617F880C" Ref="#PWR0134" Part="1"
AR Path="/6187BF05/617F880C" Ref="#PWR0136" Part="1"
AR Path="/6189E1B8/617F880C" Ref="#PWR0138" Part="1"
AR Path="/618AD774/617F880C" Ref="#PWR0140" Part="1"
AR Path="/618BDD8A/617F880C" Ref="#PWR0142" Part="1"
AR Path="/6191B1A4/617F880C" Ref="#PWR0144" Part="1"
AR Path="/61921364/617F880C" Ref="#PWR0146" Part="1"
AR Path="/61962662/617F880C" Ref="#PWR?" Part="1"
AR Path="/6196C12E/617F880C" Ref="#PWR0148" Part="1"
F 0 "#PWR0148" H 5600 3250 50 0001 C CNN
F 1 "VDD" H 5615 3573 50 0000 C CNN
F 2 "" H 5600 3400 50 0001 C CNN
F 3 "" H 5600 3400 50 0001 C CNN
1 5600 3400
1 0 0 -1
$EndComp
Text HLabel 4950 3700 0 50 Input ~ 0
in
Text HLabel 5850 3700 2 50 Output ~ 0
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Text GLabel 5150 3900 0 50 Input ~ 0
CK
$EndSCHEMATC

3
fp-lib-table Normal file
View File

@ -0,0 +1,3 @@
(fp_lib_table
(lib (name adder)(type KiCad)(uri ${KIPRJMOD}/adder.pretty)(options "")(descr ""))
)

105
nmos.sch Normal file
View File

@ -0,0 +1,105 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 27 43
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Device:Q_NMOS_GSD Q6
U 1 1 617FD6EC
P 5350 4100
AR Path="/617FD278/617FD6EC" Ref="Q6" Part="1"
AR Path="/61801128/617FD6EC" Ref="Q7" Part="1"
AR Path="/6180167A/617FD6EC" Ref="Q8" Part="1"
AR Path="/61801B8B/617FD6EC" Ref="Q9" Part="1"
AR Path="/618020CC/617FD6EC" Ref="Q10" Part="1"
AR Path="/617F2465/617FD6EC" Ref="Q16" Part="1"
AR Path="/617F3F28/617FD6EC" Ref="Q17" Part="1"
AR Path="/617F542F/617FD6EC" Ref="Q18" Part="1"
AR Path="/617F68DA/617FD6EC" Ref="Q19" Part="1"
AR Path="/6180E2AE/617FD6EC" Ref="Q20" Part="1"
AR Path="/618F6378/617FD6EC" Ref="Q24" Part="1"
AR Path="/61902300/617FD6EC" Ref="Q25" Part="1"
AR Path="/61902305/617FD6EC" Ref="Q26" Part="1"
AR Path="/6196265E/617FD6EC" Ref="Q?" Part="1"
AR Path="/6196C12A/617FD6EC" Ref="Q28" Part="1"
F 0 "Q28" H 5554 4146 50 0000 L CNN
F 1 "N" H 5554 4055 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-523" H 5550 4200 50 0001 C CNN
F 3 "~" H 5350 4100 50 0001 C CNN
1 5350 4100
1 0 0 -1
$EndComp
Text HLabel 5450 3900 2 50 Input ~ 0
source
Text HLabel 5600 4300 2 50 Output ~ 0
drain
Text HLabel 5150 4100 0 50 Input ~ 0
gate
$Comp
L Device:LED D6
U 1 1 617FF64C
P 5150 4250
AR Path="/617FD278/617FF64C" Ref="D6" Part="1"
AR Path="/61801128/617FF64C" Ref="D7" Part="1"
AR Path="/6180167A/617FF64C" Ref="D8" Part="1"
AR Path="/61801B8B/617FF64C" Ref="D9" Part="1"
AR Path="/618020CC/617FF64C" Ref="D10" Part="1"
AR Path="/617F2465/617FF64C" Ref="D16" Part="1"
AR Path="/617F3F28/617FF64C" Ref="D17" Part="1"
AR Path="/617F542F/617FF64C" Ref="D18" Part="1"
AR Path="/617F68DA/617FF64C" Ref="D19" Part="1"
AR Path="/6180E2AE/617FF64C" Ref="D20" Part="1"
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AR Path="/6196265E/617FF64C" Ref="D?" Part="1"
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F 0 "D28" V 5189 4132 50 0000 R CNN
F 1 "L" V 5098 4132 50 0000 R CNN
F 2 "LED_SMD:LED_0402_1005Metric" H 5150 4250 50 0001 C CNN
F 3 "~" H 5150 4250 50 0001 C CNN
1 5150 4250
0 -1 -1 0
$EndComp
$Comp
L Device:R R6
U 1 1 618000C0
P 5300 4400
AR Path="/617FD278/618000C0" Ref="R6" Part="1"
AR Path="/61801128/618000C0" Ref="R7" Part="1"
AR Path="/6180167A/618000C0" Ref="R8" Part="1"
AR Path="/61801B8B/618000C0" Ref="R9" Part="1"
AR Path="/618020CC/618000C0" Ref="R10" Part="1"
AR Path="/617F2465/618000C0" Ref="R24" Part="1"
AR Path="/617F3F28/618000C0" Ref="R25" Part="1"
AR Path="/617F542F/618000C0" Ref="R26" Part="1"
AR Path="/617F68DA/618000C0" Ref="R27" Part="1"
AR Path="/6180E2AE/618000C0" Ref="R28" Part="1"
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AR Path="/61902305/618000C0" Ref="R34" Part="1"
AR Path="/6196265E/618000C0" Ref="R?" Part="1"
AR Path="/6196C12A/618000C0" Ref="R36" Part="1"
F 0 "R36" V 5093 4400 50 0000 C CNN
F 1 "68" V 5184 4400 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 5230 4400 50 0001 C CNN
F 3 "~" H 5300 4400 50 0001 C CNN
1 5300 4400
0 1 1 0
$EndComp
Wire Wire Line
5450 4400 5450 4300
Wire Wire Line
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Connection ~ 5450 4300
$EndSCHEMATC

112
pmos.sch Normal file
View File

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EESchema Schematic File Version 4
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Sheet 2 43
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
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$EndDescr
Wire Wire Line
5750 4500 5750 4050
$Comp
L Device:LED D?
U 1 1 617F3A70
P 5450 3700
AR Path="/617F3A70" Ref="D?" Part="1"
AR Path="/617F1E57/617F3A70" Ref="D1" Part="1"
AR Path="/617F496C/617F3A70" Ref="D2" Part="1"
AR Path="/617F49C9/617F3A70" Ref="D3" Part="1"
AR Path="/617FA69E/617F3A70" Ref="D4" Part="1"
AR Path="/617FA71E/617F3A70" Ref="D5" Part="1"
AR Path="/617EA119/617F3A70" Ref="D11" Part="1"
AR Path="/617EB758/617F3A70" Ref="D12" Part="1"
AR Path="/617ECBC3/617F3A70" Ref="D13" Part="1"
AR Path="/617EDFF6/617F3A70" Ref="D14" Part="1"
AR Path="/617EF7A1/617F3A70" Ref="D15" Part="1"
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AR Path="/61962659/617F3A70" Ref="D?" Part="1"
AR Path="/6196C125/617F3A70" Ref="D27" Part="1"
F 0 "D1" V 5489 3582 50 0000 R CNN
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F 2 "LED_SMD:LED_0402_1005Metric" H 5450 3700 50 0001 C CNN
F 3 "~" H 5450 3700 50 0001 C CNN
1 5450 3700
0 -1 -1 0
$EndComp
$Comp
L Device:R R?
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P 5600 3550
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AR Path="/617F1E57/617F3A76" Ref="R1" Part="1"
AR Path="/617F496C/617F3A76" Ref="R2" Part="1"
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AR Path="/61962659/617F3A76" Ref="R?" Part="1"
AR Path="/6196C125/617F3A76" Ref="R35" Part="1"
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F 1 "68" H 5670 3505 50 0000 L CNN
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F 3 "~" H 5600 3550 50 0001 C CNN
1 5600 3550
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$EndComp
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Text HLabel 5450 3850 0 50 Input ~ 0
gate
$Comp
L Device:Q_PMOS_GSD Q2
U 1 1 6181BDCD
P 5650 3850
AR Path="/617F496C/6181BDCD" Ref="Q2" Part="1"
AR Path="/617F1E57/6181BDCD" Ref="Q1" Part="1"
AR Path="/617F49C9/6181BDCD" Ref="Q3" Part="1"
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AR Path="/61962659/6181BDCD" Ref="Q?" Part="1"
AR Path="/6196C125/6181BDCD" Ref="Q27" Part="1"
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F 1 "P" H 5855 3895 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-523" H 5850 3950 50 0001 C CNN
F 3 "~" H 5650 3850 50 0001 C CNN
1 5650 3850
1 0 0 1
$EndComp
$EndSCHEMATC