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Stuff, also changed to kicad 6

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This commit is contained in:
Lynn Ochs 2021-11-26 07:52:54 +01:00
parent a7fd085389
commit ea367dd2fc
12 changed files with 26365 additions and 10255 deletions
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17
adder-cache.lib
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@ -75,6 +75,23 @@ X Pin_4 4 200 -200 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x01
#
DEF Connector_Generic_Conn_01x01 J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Generic_Conn_01x01" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 5 0 -5 1 1 6 N
S -50 50 50 -50 1 1 10 f
X Pin_1 1 -200 0 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N

29819
adder.kicad_pcb
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601
adder.kicad_pro Normal file
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@ -0,0 +1,601 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 3.2,
"height": 6.4,
"width": 6.4
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.3
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
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"max_error": 0.005,
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],
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},
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"boards": [],
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"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
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"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
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"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
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"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
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"wire_dangling": "error"
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}
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3447
adder.kicad_sch Normal file
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239
adder.pro
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@ -1,239 +0,0 @@
update=Sun 31 Oct 2021 04:47:34 PM CET
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.5
ViaDiameter1=0.6
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=1
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

1220
adder.sch
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233
buffer.kicad_sch Normal file
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@ -0,0 +1,233 @@
(kicad_sch (version 20210621) (generator eeschema)
(uuid 9d4aace8-7a3b-4c69-ae62-6e20c4e7b9ee)
(paper "A4")
(lib_symbols
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(effects (font (size 1.27 1.27)) hide)
)
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(effects (font (size 1.27 1.27)) hide)
)
(property "ki_keywords" "Single D Flip-Flop D CMOS" (id 4) (at 0 0 0)
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(property "ki_description" "Single D Flip-Flop, Low-Voltage CMOS" (id 5) (at 0 0 0)
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AR Path="/6188F5BD/617F3A76" Ref="R30" Part="1"
AR Path="/61894615/617F3A76" Ref="R?" Part="1"
AR Path="/6189461A/617F3A76" Ref="R31" Part="1"
AR Path="/61962659/617F3A76" Ref="R?" Part="1"
AR Path="/6196C125/617F3A76" Ref="R35" Part="1"
F 0 "R1" H 5670 3596 50 0000 L CNN
F 1 "68" H 5670 3505 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 5530 3550 50 0001 C CNN
F 3 "~" H 5600 3550 50 0001 C CNN
1 5600 3550
0 -1 -1 0
$EndComp
Wire Wire Line
5750 3650 5750 3550
Wire Wire Line
5750 3550 5750 3300
Connection ~ 5750 3550
Text HLabel 5750 3300 0 50 Input ~ 0
source
Text HLabel 5750 4500 2 50 Output ~ 0
drain
Text HLabel 5450 3850 0 50 Input ~ 0
gate
$Comp
L Device:Q_PMOS_GSD Q2
U 1 1 6181BDCD
P 5650 3850
AR Path="/617F496C/6181BDCD" Ref="Q2" Part="1"
AR Path="/617F1E57/6181BDCD" Ref="Q1" Part="1"
AR Path="/617F49C9/6181BDCD" Ref="Q3" Part="1"
AR Path="/617FA69E/6181BDCD" Ref="Q4" Part="1"
AR Path="/617FA71E/6181BDCD" Ref="Q5" Part="1"
AR Path="/617EA119/6181BDCD" Ref="Q11" Part="1"
AR Path="/617EB758/6181BDCD" Ref="Q12" Part="1"
AR Path="/617ECBC3/6181BDCD" Ref="Q13" Part="1"
AR Path="/617EDFF6/6181BDCD" Ref="Q14" Part="1"
AR Path="/617EF7A1/6181BDCD" Ref="Q15" Part="1"
AR Path="/6188A626/6181BDCD" Ref="Q21" Part="1"
AR Path="/6188F5BD/6181BDCD" Ref="Q22" Part="1"
AR Path="/61894615/6181BDCD" Ref="Q?" Part="1"
AR Path="/6189461A/6181BDCD" Ref="Q23" Part="1"
AR Path="/61962659/6181BDCD" Ref="Q?" Part="1"
AR Path="/6196C125/6181BDCD" Ref="Q27" Part="1"
F 0 "Q1" H 5855 3804 50 0000 L CNN
F 1 "P" H 5855 3895 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-523" H 5850 3950 50 0001 C CNN
F 3 "~" H 5650 3850 50 0001 C CNN
1 5650 3850
1 0 0 1
$EndComp
$EndSCHEMATC